This invention relates to a semiconductor integrated circuit device and a method of producing the same. More particularly, the present invention relates to integrated circuit devices such as an application specific I.C. (ASIC), a microprocessor, a microcontroller, a digital signal processor, etc., and a method of efficiently producing them.
Systems such as gate arrays, standard cells, cell based ICs, etc., have been widely employed in the past to accomplish a large-scale logic circuit, in particular. A characteristic feature of these integrated circuits is that partial circuits referred to as xe2x80x9ccellsxe2x80x9d are prepared in advance.
The term xe2x80x9ccellxe2x80x9d means a small scale logic circuit such as NAND, NOR, etc., for which layout of a mask pattern has already been finished. Generally, the positions of input/output terminals and an operation speed are determined besides the mask layout.
When information on this cell is gathered and registered to an auxiliary memory unit of a computer for computer aided design, it is referred to as a xe2x80x9ccell libraryxe2x80x9d (or sometimes xe2x80x9cmacrocell libraryxe2x80x9d, xe2x80x9cmacro libraryxe2x80x9d, xe2x80x9cdevice libraryxe2x80x9d and xe2x80x9cstandard cell libraryxe2x80x9d).
If such a cell library for so-called xe2x80x9cCAD (Computer Aided Design)xe2x80x9d is prepaid in advance, an integrated circuit having an intended logic function can be accomplished by merely disposing the cells on a chip and connecting the terminals of the cells by wirings. Accordingly, the integrated circuit having the intended logic function can be fabricated within a short time because logic design can be carried out without taking a circuit operation on a transistor level and layout into consideration.
A xe2x80x9cpass transistor circuitxe2x80x9d is another technology associated with the present invention. It is known that when the pass transistor circuits are used, logic such as 2-input AND, OR, exclusive-OR (XOR), etc., can be accomplished in a smaller area and at a higher speed than ordinary CMOS circuits by using the same internal circuit connection and changing the application forms of external 2-input signals and their inverted 2-input signals (that is, two complementary input signals).
A publication, J. H. Pasternak et al IEEE Circuits and Devices, July, 1993, pp. 23-28 and a publication K. Yano et al IEEE Journal of Solid-State Circuits, Vol. 25, No. 2, pp. 388-395 (1990) can be cited as the references relating to this pass transistor circuit.
These references describe that in order to constitute 3-input OR, AND, XOR, etc., by using the means of this pass transistor circuit, the internal circuit connection for constituting XOR is different from the internal connection for constituting OR and AND, and that the application form of the 3-input signal for constituting XOR is different from the application form of the 3-input signal for constituting OR and AND.
On the other hand, the article xe2x80x9cSpeed Performance of Pass Transistor Logic Gate Using CMOS/SIMOX Processxe2x80x9d by Y. Kado et al, 1992 The Institute of Electronics Information and Communication Engineers of Japan, Spring Meeting, C-560, pp. 5-181 describes a 2-input NAND/AND gate circuit having improved speed performance wherein an inverter for amplifying an output voltage is connected to a source-drain path of a pass transistor, and when the drain and the gate of one pass transistor are driven by complementary input signals or by the same input signal, speed performance can be improved by setting the drain input signal to a ground level Vss or to a power supply voltage level VDD.
When logics of a plurality of cells used in a large-scale logic integrated circuit such as a conventional gate array, a standard cell, etc., are different, the internal circuit connection becomes naturally different.
Therefore, a cell library for accomplishing a large-scale logic integrated circuit generally contains a great number of cells such as sixty or more cells. A great deal of labor are necessary to prepare such a large number of cells. For, it is necessary to determine the internal circuit connection and the positions of the input/output terminals for each of the cells, to execute mask layout and to evaluate a delay time. If the number of cells is reduced so as to reduce this labor, the necessary logics are not prepared as the cells in many cases. In such cases, two or more cells must be combined to accomplish the required logics. As a result, the area of the integrated circuit and its delay time as well as power consumption becomes great. In other words, the reduction of the number of cells registered is not a realistic solution from the aspect of performance.
It is further noteworthy that even when a large number of cells such as at least sixty cells are prepared, only a part of the logic functions practically used can be accomplished. For example, 3-input logics are 256 kinds in all and 4-input logics are as great as 65,536 kinds. Accordingly, even when a simple logic such as 3-input or 4-input is accomplished, the logic function must be practically accomplished by combining a large number of cells of the cell library. The integrated circuit accomplished by the combination of the cells is not always most suitable for the intended logic function, and is inferior to an optimum circuit in every aspects of the speed, the area and power consumption.
The J. H. Pasternak et al reference described above discloses a method of accomplishing logic function, based on standard cells, such as 3-input OR, AND and XOR, using the pass transistor circuit. The standard cell for accomplishing the 2-input and 3-input OR and AND logics accomplished by the present inventors on the basis of the information disclosed in this reference are shown in FIGS. 5A to 5C of the accompanying drawings. In other words, the circuit construction shown in FIGS. 5A to 5C are not known in the art. Since the input of this cell is the 2-input or 3-input, an inverter for signal inversion must be disposed inside the cell. Therefore, a logic circuit for accomplishing the OR or AND logic using the pass transistor can be provided by carrying out in advance layout of the mask pattern such as the source-drain region, the gate electrode, etc., of the transistor of the cell internal or inside circuit shown in FIG. 5A and then effecting the internal connection of this cell. A simple example is shown in FIGS. 5B and 5C.
However, the logic functions accomplished in a cell library shown in FIG. 5A is the same as that accomplished in the conventional standard cell library, such as AND and OR. Therefore, the cost of preparing the library is not reduced.
In addition, since the source-drain path of the pass transistor is directly coupled to the output terminal of the cell in this cell, the driving capacity of the cell output is limited by the ON resistance of the pass transistor. Particularly because the source-drain paths of the two pass transistors are connected in series between the input terminal and the output terminal in the 3-input circuit, the driving capacity of this cell output is extremely low.
Because the inverter for inverting the signal must be disposed in this cell, the cell involves the problem that the cell area is great.
In the pass transistor circuits disclosed in the K. Yano et al and Y. Kado et al reference described above, on the other hand, a plurality of complementary input signals are applied, so that the inverter for signal inversion is eliminated inside the circuit, and an inverter for amplifying an output voltage is coupled to the source-drain path of the pass transistor. However, these references do not teach or suggest the concept of using this pass transistor circuit for the cell of the cell library for CAD.
A semiconductor circuit according to an embodiment of the present invention includes a first cell (31 in FIG. 3) and a second cell (32 in FIG. 3) disposed at different positions on a semiconductor chip, wherein:
each of the first and second cells has a substantially square shape and includes first, second, third and fourth active devices (M13 to M16 in FIG. 1), a first node (N3), a second node (N4), first, second, third, fourth, fifth, sixth and seventh input terminals (15 to 21) and an output terminal (22);
in each of the first and second cells,
a gate electrode of the first active device (M13) is coupled to the first input terminal (15);
a gate electrode of the second active device (M14) is coupled to the second input terminal (16);
a gate electrode of the third active device (M15) is coupled to the third input terminal (17);
a gate electrode of the fourth active device (M16) is coupled to the fourth input terminal (18);
a source-drain path of the first active device is coupled between the first node and the seventh input terminal;
a source-drain path of the second active device is coupled between the first node and the second node;
a source-drain path of the third active device is coupled between the second node and the sixth input terminal;
a source-drain path of the fourth active device is coupled between the second node and the fifth input terminal;
the second node is coupled to the output terminal;
disposition of the active devices and the input/output terminals inside the first cell is substantially the same as disposition of the active devices and the input/output terminals inside the second cell; and
circuit connection of the active devices and circuit connection of the input/output terminals inside the first cell are substantially the same as circuit connection of the active devices and circuit connection of the input/output terminals inside the second cell;
in one of the first and second cells,
a first input signal (A) is applied to the first input terminal from outside the cell;
a second input signal (AN) having an opposite phase to that of the first input signal is applied to the second input terminal from outside the cell;
a third input signal (B) is applied to the third input terminal from outside the cell;
a fourth input signal (BN) having an opposite phase to that of the third input signal is applied to the fourth input terminal from outside the cell; and
signals ((C,D,E) N, Vcc) different from the first, second, third and fourth input signals (A, AN, B, BN) are applied to at least two input signals (19, 20) among the fifth, sixth and seventh input terminals from outside the cell.
A semiconductor integrated circuit according to another embodiment of the present invention includes a first cell (31 in FIG. 3) and a second cell (32 in FIG. 3) disposed at different positions on a semiconductor chip, and wherein:
each of the first and second cells has a substantially square shape and includes first, second, third and fourth active devices (M13, M14, M15, M16 in FIG. 1), first and second inverters, a first node (N3), a second node (N4), first, second, third, fourth and fifth input terminals (16, 18, 19, 20, 21) and an output terminal;
in each of the first and second cells,
a gate electrode of the second active device is coupled to the first input terminal;
a gate electrode of the fourth active device is coupled to the second input terminal;
an input and an output of the first inverter are coupled to the first input terminal and to the gate electrode of the first active device, respectively;
an input and an output of the second inverter are coupled to the second input terminal and to the gate electrode of the third active device, respectively;
a source-drain path of the first active device is coupled between the first node and the fifth input terminal;
a source-drain path of the second active device is coupled between the first node and the second node;
a source-drain path of the third active device is coupled between the second node and the fourth input terminal;
a source-drain path of the fourth active device is coupled between the second node and the third input terminal;
the first node is coupled to the output terminal;
disposition of the active devices and the input/output terminals inside the first cell is substantially the same as disposition of the active devices and the input/output terminals inside the second cell;
circuit connection of the active devices and the input/output terminals inside the first cell is substantially the same as circuit connection of the active devices and circuit connection of the active devices and the input/output terminals inside the second cell;
in one of the first and second cells,
a first input signal (AN) is applied to the first input terminal from outside the cell;
a second input signal (BN) is applied to the second input terminal from outside the cell; and
signals ((C,D,E) N, Vcc) different from the first and second input signals (AN, BN) are applied to at least two input terminals (19, 20) among the third, fourth and fifth input terminals from outside the cell.
A semiconductor integrated circuit according to a concrete embodiment of the present invention is constituted in such a manner that the first and second cells described above can change the logical output obtained from the output terminal by changing the signal application forms to the first, second, third, fourth, fifth, sixth and seventh input terminals.
A semiconductor integrated circuit according to another concrete embodiment of the present invention has an output amplification circuit (I5 in FIG. 1), a first operation potential supply line to which a first operation voltage (Vcc) is supplied and a second operation supply line to which a second operation potential (GND) is supplied, inside the first and the second cells described above, and wherein an operation potential is supplied to the output amplification circuit when it is coupled to the first and second operation potential supply lines, an input and an output of the output amplification circuit are coupled to the first node and to the output terminal, respectively, the output amplification circuit is disposed at substantially the same position inside each of the cells and the output amplification circuit has substantially the same circuit connection by wirings in each of the cells.
A semiconductor integrated circuit according to still another concrete embodiment of the present invention includes a first layer wiring, a second layer wiring and a third layer wiring, and wherein the first layer wiring couples the active devices and the input/output terminals in each of the first and second cells, and the second layer wiring or the third layer wiring supplies the first, second, third and fourth input signals to the first, second, third and fourth input terminals, respectively, and couples the first cell to the second cell.
A semiconductor integrated circuit according to still another concrete embodiment of the present invention has the structure wherein among the fifth, sixth and seventh input terminals of one of the cells to which the different signals are applied, at least one of these input terminals is coupled to the first operation potential supply line or the second operation potential supply line.
A semiconductor integrated circuit according to still another concrete embodiment of the present invention has the structure wherein the first operation potential supply line and the second operation potential supply line are disposed substantially in parallel with each other, and the first, second, third and fourth active devices and the output amplification circuit are disposed between the first operation potential supply line and the second operation potential supply line.
In a semiconductor integrated circuit according to still another concrete embodiment of the present invention, the longitudinal direction of the gate electrodes of the first, second, third and fourth active devices and the gate electrodes of the two active devices constituting the output amplification circuit are disposed in a direction crossing substantially orthogonally the longitudinal direction of the first and second potential supply lines.
In a semiconductor integrated circuit according to still another concrete embodiment of the present invention, each of the two active devices constituting the output amplification circuit comprises a plurality of active devices having the gate electrodes thereof connected in common and the source-drain paths thereof connected in parallel.
A method of producing a semiconductor integrated circuit including the cell according to an embodiment of the present invention described above comprises:
a first step of registering in advance the positions of the input terminals of the cell, the position of the output terminal and disposition of the active devices to memory means of a computer;
a second step of reading out the positions of the input terminals, the position of the output terminal and disposition of the active devices registered at the first step from the memory means, and designating the application form of external signals to the input terminals so read out; and
a third step of transferring a layout pattern to a semiconductor substrate in accordance with the signal application form designated at the second step (refer to FIG. 24).
In a production method of a semiconductor integrated circuit device according to a more concrete embodiment of the present invention, the second step described above is a step which decides a logic function of the cell by designating the signal application form to the input terminals.
In a production method of a semiconductor integrated circuit device according to a more concrete embodiment of the present invention, the first step is a step which executes registration for at least two cells, the second step is a step which reads out information of at least two cells from the memory means and designates the signal application form of external signals to the input terminals so read out, and the method further includes a step of designating the positions of a plurality of cells on a chip and wirings between the input terminals and between the cells on the basis of the signal application form designated by the second step.
The semiconductor integrated circuit according to one embodiment of the present invention can accomplish various intended logics by merely changing the application forms of a plurality of input signals to the first input terminal (15), the second input terminal (16), the third input terminal (17), the fourth input terminal (18), the fifth input terminal (19), the sixth input terminal (20) and the seventh input terminal (21) outside each cell, even when the first cell (31 in FIG. 3) and the second cell (32 in FIG. 3) have substantially the same internal circuit connection and substantially the same disposition of the internal circuit devices. Needless to say, the higher independence of a plurality of input signals, the more complicated logics can be accomplished.
Because the input and the output of the output amplification circuit (I5) are connected to the first node (N3) and to the output terminal (22) inside the cell, respectively, the output driving capacity of the cell can be increased.
In the other cell (32 in FIG. 3), on the other hand, the first input signal (A) is applied from outside the cell to the first input terminal (15), the second input signal (AN) having the opposite phase to the first input signal (A) is applied from outside the cell to the second input terminal (16), the third input signal (B) is applied from outside the cell to the third input terminal (17) and the fourth input signal (AN) having the opposite phase to the third input signal (B) is applied from outside the cell to the fourth input terminal (18). Accordingly, the inverter for inverting the input signals is eliminated inside the cell. As a result, the cell area can be reduced.
In the semiconductor integrated circuit according to another embodiment of the present invention, the first and second inverters for inverting the input signals are disposed inside the cell. Accordingly, though the cell area increases to some extents, the complementary input signals need not be applied from outside the cell, so that the area of the wiring channel outside the cell can be reduced.
The semiconductor integrated circuit according to one embodiment of the present invention includes the first operation potential supply line (Vcc) and the second operation potential supply line (GND) for supplying the operation potentials to the output amplification circuit (I5) for improving the output driving capacity inside the cell. One of the cells (32 in FIG. 3) can accomplish the intended logic when any of the first, second, third and fourth input signals (A, AN, B, BN) is appropriately applied to the sixth input terminal (20) and the seventh input terminal (21) from outside the cell. As represented in the concrete embodiment of the present invention, however, the same intended logic can be accomplished by applying the fixed potential of either the first operation potential supply line (Vcc) or the second operation potential supply line (GND) to the sixth input terminal (20) and to the seventh input terminal (21) of one of the cells. The application of the fixed potential in this way can reduce the driving load of the application of a plurality of input signals from a prestage circuit to one of the cells, and can improve speed performance.
In the semiconductor integrated circuit according to a more concrete embodiment of the present invention, the first, second, third and fourth active devices (M13, M14, M15, M16) and the output amplification circuit (I5) of one of the cells are disposed between the first operation potential supply line (Vcc) and the second operation potential supply line (GND) that are disposed substantially in parallel with each other. Accordingly, the fixed potential of either the first operation potential supply line (Vcc) or the second operation potential supply line (GND) can be easily applied to the sixth input terminal (20) and the seventh terminal (21) of one of the cells by the wiring which crosses substantially orthogonally the first operation potential supply line (Vcc) and the second operation potential supply line (GND).
In the semiconductor integrated circuit according to a more concrete embodiment of the present invention, a special contrivance is made to the disposition of the longitudinal direction of the first operation potential line (Vcc) and the second operation potential supply line (GND) and to the disposition of the gate electrodes of the first active device (M13), the second active device (M14), the third active device (Ml5), the fourth active device (M16) and the two active devices (Mp, MN) constituting the output amplification circuit (I5). Accordingly, the semiconductor integrated circuit can be accomplished in a smaller cell area (see FIG. 1).
In the semiconductor integrated circuit according to a more concrete embodiment of the present invention, each of the two active devices (Mp, MN) constituting the output amplification circuit (5) comprises a plurality of active devices connected in parallel. Accordingly, the output driving capacity of this output amplification circuit (I5) can be increased irrespective of the small cell area (see FIG. 1).
A production method of a semiconductor integrated circuit according to an embodiment of the present invention (see FIG. 24) makes it possible to conduct computer aided design (CAD) of a semiconductor integrated circuit containing the cells having the advantages described above, and to practically produce the semiconductor integrated circuit by this design.
The present invention is completed in the development of a large-scale logic integrated circuit capable of accomplishing the intended logics by merely changing the forms of application of a plurality of input signals from outside the cells in accordance with the intended logics by making the same the internal circuits of the cells for accomplishing various logics in an integrated circuit designed by using the cell library for the CAD.
It is an object of the present invention to furnish cells of a large-scale logic integrated circuit of this kind with a large driving capacity and to improve speed performance.
It is another object of the present invention to provide a semiconductor integrated circuit device capable of accomplishing various intended logics by merely changing the signal application form to input terminals of cells.
It is still another object of the present invention to provide a semiconductor integrated circuit device which improves the output driving capacity of the cells described above.
It is still another object of the present invention to provide a semiconductor integrated circuit device which reduces the occupying area of the cells described above.
It is still another object of the present invention to provide a semiconductor integrated circuit device which reduces a wiring channel area outside the cells described above.
It is still another object of the present invention to provide a semiconductor integrated circuit device which reduces a driving load of input signals to the cells described above and improves speed performance.
It is a further object of the present invention to make it possible to conduct CAD design of a semiconductor integrated circuit inclusive of the cells described above, and to produce the semiconductor integrated circuit on the basis of the design.